The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
Photoresist materials are coated onto the surface of a wafer by dispensing a photoresist fluid typically on the center of the wafer as the wafer rotates at high speeds within a stationary bowl or coater cup. The coater cup catches excess fluids and particles ejected from the rotating wafer during application of the photoresist. The photoresist fluid dispensed onto the center of the wafer is spread outwardly toward the edges of the wafer by surface tension generated by the centrifugal force of the rotating wafer. This facilitates uniform application of the liquid photoresist on the entire surface of the wafer.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
During the photolithography step of semiconductor production, light energy is applied through a reticle mask onto the photoresist material previously deposited on the wafer to define circuit patterns which will be etched in a subsequent processing step to define the circuits on the wafer. Because these circuit patterns on the photoresist represent a two-dimensional configuration of the circuit to be fabricated on the wafer, minimization of particle generation and uniform application of the photoresist material to the wafer are very important. By minimizing or eliminating particle generation during photoresist application, the resolution of the circuit patterns, as well as circuit pattern density, is increased.
A reticle is a transparent plate patterned with a circuit image to be formed in the photoresist coating on the wafer. A reticle contains the circuit pattern image for only a few of the die on a wafer, such as four die, for example, and thus, must be stepped and repeated across the entire surface of the wafer. In contrast, a photomask, or mask, includes the circuit pattern image for all of the die on a wafer and requires only one exposure to transfer the circuit pattern image for all of the dies to the wafer.
Spin coating of photoresist on wafers, as well as the other steps in the photolithography process, is carried out in an automated coater/developer track system using wafer handling equipment which transport the wafers between the various photolithography operation stations, such as vapor prime resist spin coat, develop, baking and chilling stations. Robotic handling of the wafers minimizes particle generation and wafer damage. Automated wafer tracks enable various processing operations to be carried out simultaneously. Two types of automated track systems widely used in the industry are the TEL (Tokyo Electron Limited) track and the SVG (Silicon Valley Group) track.
A typical method of forming a photoresist circuit pattern on a wafer includes introducing the wafer into the automated track system and then coating a photoresist layer onto the wafer. The photoresist is next cured by conducting a soft bake process. After it is cooled, the wafer is placed in an exposure apparatus, such as a stepper, which aligns the wafer with an array of die patterns etched on the typically chrome-coated quartz reticle. When properly aligned and focused, the stepper exposes a small area of the wafer, then shifts or “steps” to the next field and repeats the process until the entire wafer surface has been exposed to the die patterns on the reticle. After the aligning and exposing step, the wafer is exposed to post-exposure baking and then is developed, hard-baked to develop the photoresist pattern, and finally, removed from the track.
Throughout the photolithography process, the wafers are transported through a photolithography track that contains the various processing stations. A portion of a typical conventional photolithography track 10 is schematically shown in FIG. 1 and includes a track interface 12 which interfaces with a stepper 22. The track interface 12 contains a buffer cassette 14 that is loaded with photoresist-coated wafers 16 to be subsequently exposed in the stepper 22. A wafer transfer robot 18 transfers the wafers 16 from the buffer cassette 14 into the stepper 22. A wafer edge aligner (WEE) 20 is typically included in the track interface 12.
The stepper 22 contains a pre-alignment chamber 23 in which is provided an OF table 24. A wafer stage 32 is provided in the stepper 22, and a wafer transfer robot 30 is positioned between the OF table 24 and the wafer stage 32. In operation, the wafer transfer robot 18 in the track interface 12 places a wafer 28 onto a shaft 26 extended from the center of the OF table 24, after which the shaft 26 retracts and lowers the wafer 28 onto the OF table 24. The wafer 28 remains on the OF table 24 while a wafer 34 on the wafer stage 32 is aligned and exposed light through a reticle (not shown) in a stepped and repeated procedure for the formation of circuit patterns on the photoresist on the wafer 34. After the exposure procedure is completed and the wafer 34 is removed from the wafer stage 32 for further processing in a downstream processing station, the wafer transfer robot 30 transfers the wafer 28 from the OF table 24 to the wafer stage 32 for alignment and stepped exposure of the wafer 28 in similar fashion.
One of the problems inherent in the temporary storage of the wafers 16 in the buffer cassette 14 inside the track interface 12 is that the WEE 20 generates a substantial quantity of heat inside the track interface 12. This causes a rise in temperature inside the track interface 12 on the order of about 1-2 degrees Celsius. Typically, the temperature of the wafers 16 upon entry into the track interface 12 is about 23° C., and the wafers 16 may be warmed to a temperature of up to about 24-25° C. upon transfer to the OF table 24. While on the wafer stage 32, each wafer is maintained at a temperature of typically about 22.5° C. Accordingly, upon placement of each wafer on the wafer stage 32, the wafer may be several degrees warmer than the wafer stage 32. This disparity in temperatures causes a difference in temperatures between the core and the surface of the wafer, contributing to Nikon overlay and SMP (symmetrical multiprocessing) instability frequently leading to product failure. While an electric fan (not shown) typically provided in the track interface 12 is capable of reducing the interface temperature inside the track interface 12 somewhat, this reduction in temperature is inadequate for optimally maintaining the wafers 16 in the buffer cassette 14 at the same temperature as the wafer stage 32. Accordingly, an apparatus is needed for uniformly cooling and maintaining a wafer at substantially the same temperature as that of a wafer stage in a stepper before the wafer is transferred to the wafer stage. Such an apparatus would impart a substantially uniform temperature among all regions, particularly the core and surface regions, of the wafer and enhance Nikon overlay and SMP focus stability during alignment and exposure of the wafer through the reticle.
An object of the present invention is to provide an apparatus for maintaining a wafer at substantially the same temperature as a wafer stage in a stepper prior to transfer of the wafer to the wafer stage.
Another object of the present invention is to provide an apparatus and method which contributes to stability in Nikon overlay and SMP focus in the fabrication of semiconductor integrated circuits.
Still another object of the present invention is to provide an apparatus and method which facilitates uniform temperatures among all regions on a wafer prior to the exposure step in a photolithography process.
Yet another object of the present invention is to provide an apparatus and method which is suitable for reducing temperature gradients in a wafer during alignment of a wafer to an array of die patterns on a reticle and exposure of the wafer to light through the reticle in the formation of circuit patterns on the wafer.
Yet another object of the present invention is to provide an apparatus and method which facilitates optimum control of temperatures throughout a wafer.
A still further object of the present invention is to provide an apparatus for maintaining a wafer at an optimum temperature for a semiconductor fabrication process, which apparatus includes a cooling plate for receiving the wafer and maintaining the wafer at the optimum temperature.